Signal Processing

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Bit-width of the component port and its connected net must match.

Last post by mamorani « Sat Mar 13, 2021 9:43 am

by mamorani » Sat Mar 13, 2021 9:43 am

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360 Views

Last post by mamorani
Sat Mar 13, 2021 9:43 am
Only one port or signal declaration should be in one line.

Last post by mamorani « Sat Mar 13, 2021 9:42 am

by mamorani » Sat Mar 13, 2021 9:42 am

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276 Views

Last post by mamorani
Sat Mar 13, 2021 9:42 am
The order of module port declarations and instance port connection lists should be same as the order in the module port

Last post by mamorani « Sat Mar 13, 2021 9:42 am

by mamorani » Sat Mar 13, 2021 9:42 am

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312 Views

Last post by mamorani
Sat Mar 13, 2021 9:42 am
Do not use embedded dc_shell scripts in the design

Last post by mamorani « Sat Mar 13, 2021 9:42 am

by mamorani » Sat Mar 13, 2021 9:42 am

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286 Views

Last post by mamorani
Sat Mar 13, 2021 9:42 am
Exit or next statement must not be used in a for loop

Last post by mamorani « Sat Mar 13, 2021 9:41 am

by mamorani » Sat Mar 13, 2021 9:41 am

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308 Views

Last post by mamorani
Sat Mar 13, 2021 9:41 am
Separate for loops must be used in reset and logic parts of flip-flop descriptions.

Last post by mamorani « Sat Mar 13, 2021 9:41 am

by mamorani » Sat Mar 13, 2021 9:41 am

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296 Views

Last post by mamorani
Sat Mar 13, 2021 9:41 am
Terminating condition of "for" constructs must be a constant.

Last post by mamorani « Sat Mar 13, 2021 9:39 am

by mamorani » Sat Mar 13, 2021 9:39 am

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319 Views

Last post by mamorani
Sat Mar 13, 2021 9:39 am
Logical, arithmetic, bit wise or reduction operations should not be used in case construct condition

Last post by mamorani « Sat Mar 13, 2021 9:39 am

by mamorani » Sat Mar 13, 2021 9:39 am

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314 Views

Last post by mamorani
Sat Mar 13, 2021 9:39 am
Coding style of don't-care condition in casex or casez branches is not proper

Last post by mamorani « Sat Mar 13, 2021 9:38 am

by mamorani » Sat Mar 13, 2021 9:38 am

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342 Views

Last post by mamorani
Sat Mar 13, 2021 9:38 am
casex or casez constructs must contain a condition with don't care

Last post by mamorani « Sat Mar 13, 2021 9:37 am

by mamorani » Sat Mar 13, 2021 9:37 am

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277 Views

Last post by mamorani
Sat Mar 13, 2021 9:37 am
default clause in case constructs must be the last clause.

Last post by mamorani « Sat Mar 13, 2021 9:35 am

by mamorani » Sat Mar 13, 2021 9:35 am

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289 Views

Last post by mamorani
Sat Mar 13, 2021 9:35 am
Chain of if...else if construDo not use //synopsys full_case pragma when all conditions acts must not be exceed levels

Last post by mamorani « Sat Mar 13, 2021 9:34 am

by mamorani » Sat Mar 13, 2021 9:34 am

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323 Views

Last post by mamorani
Sat Mar 13, 2021 9:34 am
Chain of if...else if constructs must not be exceed levels

Last post by mamorani « Sat Mar 13, 2021 9:33 am

by mamorani » Sat Mar 13, 2021 9:33 am

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318 Views

Last post by mamorani
Sat Mar 13, 2021 9:33 am
Use "case" statements instead of if/else statements, where feasible, if performance is important.

Last post by mamorani « Sat Mar 13, 2021 9:32 am

by mamorani » Sat Mar 13, 2021 9:32 am

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363 Views

Last post by mamorani
Sat Mar 13, 2021 9:32 am
Where feasible case statements should be used rather than 'if-else' statements, if performance is important

Last post by mamorani « Sat Mar 13, 2021 9:32 am

by mamorani » Sat Mar 13, 2021 9:32 am

0 Replies

331 Views

Last post by mamorani
Sat Mar 13, 2021 9:32 am
Nesting in if-else constructs should not be deeper than the levels

Last post by mamorani « Sat Mar 13, 2021 9:31 am

by mamorani » Sat Mar 13, 2021 9:31 am

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344 Views

Last post by mamorani
Sat Mar 13, 2021 9:31 am
Do not describe more than number,integer} statements (if/case/while/for/ loop) separately within a single process block

Last post by mamorani « Sat Mar 13, 2021 9:30 am

by mamorani » Sat Mar 13, 2021 9:30 am

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320 Views

Last post by mamorani
Sat Mar 13, 2021 9:30 am
Logic directly driven by tristate nets should be in a separate module

Last post by mamorani « Sat Mar 13, 2021 9:27 am

by mamorani » Sat Mar 13, 2021 9:27 am

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324 Views

Last post by mamorani
Sat Mar 13, 2021 9:27 am
Do not enter a tristate output in the selection expression of casex and casez statement

Last post by mamorani « Sat Mar 13, 2021 9:26 am

by mamorani » Sat Mar 13, 2021 9:26 am

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355 Views

Last post by mamorani
Sat Mar 13, 2021 9:26 am
Nets other than tristate nets must not be driven by multiple drivers

Last post by mamorani « Sat Mar 13, 2021 9:25 am

by mamorani » Sat Mar 13, 2021 9:25 am

0 Replies

271 Views

Last post by mamorani
Sat Mar 13, 2021 9:25 am
Tristate descriptions must not be mixed with other descriptions in same module

Last post by mamorani « Sat Mar 13, 2021 9:25 am

by mamorani » Sat Mar 13, 2021 9:25 am

0 Replies

299 Views

Last post by mamorani
Sat Mar 13, 2021 9:25 am
Avoid combinational loops that contain latches.

Last post by mamorani « Sat Mar 13, 2021 9:25 am

by mamorani » Sat Mar 13, 2021 9:25 am

0 Replies

308 Views

Last post by mamorani
Sat Mar 13, 2021 9:25 am
Latch descriptions should not be mixed with other descriptions in same module

Last post by mamorani « Sat Mar 13, 2021 9:24 am

by mamorani » Sat Mar 13, 2021 9:24 am

0 Replies

429 Views

Last post by mamorani
Sat Mar 13, 2021 9:24 am
Do not mix descriptions of flip-flops with asynchronous reset and flip-flops without asynchronous reset in the same proc

Last post by mamorani « Sat Mar 13, 2021 9:24 am

by mamorani » Sat Mar 13, 2021 9:24 am

0 Replies

333 Views

Last post by mamorani
Sat Mar 13, 2021 9:24 am
Variables, if used, must be assigned to a signal before the end of the process

Last post by mamorani « Sat Mar 13, 2021 9:23 am

by mamorani » Sat Mar 13, 2021 9:23 am

0 Replies

334 Views

Last post by mamorani
Sat Mar 13, 2021 9:23 am

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