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All sample times for the FIFO block must be discrete. A continuous sample time was detected inside the FIFO block. This

Last post by mamorani « Sun Mar 14, 2021 9:48 pm

by mamorani » Sun Mar 14, 2021 9:48 pm

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Last post by mamorani
Sun Mar 14, 2021 9:48 pm
The HDL FIFO ''In'' and ''Push'' inputs sample times have to be times of the 'Pop' input sample time.

Last post by mamorani « Sun Mar 14, 2021 9:47 pm

by mamorani » Sun Mar 14, 2021 9:47 pm

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Last post by mamorani
Sun Mar 14, 2021 9:47 pm
The HDL FIFO only supports scalar input data.

Last post by mamorani « Sun Mar 14, 2021 9:47 pm

by mamorani » Sun Mar 14, 2021 9:47 pm

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Last post by mamorani
Sun Mar 14, 2021 9:47 pm
The FIFO in FWFT mode does not support an output sample time to input sample time ratio which is not equal to 1.

Last post by mamorani « Sun Mar 14, 2021 9:47 pm

by mamorani » Sun Mar 14, 2021 9:47 pm

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Last post by mamorani
Sun Mar 14, 2021 9:47 pm
Register size must be a scalar positive integer which is at least 4.

Last post by mamorani « Sun Mar 14, 2021 9:46 pm

by mamorani » Sun Mar 14, 2021 9:46 pm

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Last post by mamorani
Sun Mar 14, 2021 9:46 pm
The ratio of output sample rate to input sample rate must be a positive integer or 1/N, where N is a positive integer.

Last post by mamorani « Sun Mar 14, 2021 9:46 pm

by mamorani » Sun Mar 14, 2021 9:46 pm

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Last post by mamorani
Sun Mar 14, 2021 9:46 pm
Write access on either or both ports A and B to the same memory address is not supported due to undefined result in the

Last post by mamorani « Sun Mar 14, 2021 9:46 pm

by mamorani » Sun Mar 14, 2021 9:46 pm

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Last post by mamorani
Sun Mar 14, 2021 9:46 pm
The address ports of each ports bank are driven by the same signal. Possibility of undefined result in the synthesized R

Last post by mamorani « Sun Mar 14, 2021 9:45 pm

by mamorani » Sun Mar 14, 2021 9:45 pm

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Last post by mamorani
Sun Mar 14, 2021 9:45 pm
Address port width should be between and

Last post by mamorani « Sun Mar 14, 2021 9:45 pm

by mamorani » Sun Mar 14, 2021 9:45 pm

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Last post by mamorani
Sun Mar 14, 2021 9:45 pm
If you use multitasking mode, you may get incorrect simulation results for the block. Use a fixed-step, discrete solve

Last post by mamorani « Sun Mar 14, 2021 9:44 pm

by mamorani » Sun Mar 14, 2021 9:44 pm

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Last post by mamorani
Sun Mar 14, 2021 9:44 pm
The Serializer block requires input vector size to be integer multiple of output vector size

Last post by mamorani « Sun Mar 14, 2021 9:43 pm

by mamorani » Sun Mar 14, 2021 9:43 pm

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Last post by mamorani
Sun Mar 14, 2021 9:43 pm
The Serializer block requires input vector size to be integer multiple of output vector size

Last post by mamorani « Sun Mar 14, 2021 9:43 pm

by mamorani » Sun Mar 14, 2021 9:43 pm

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Last post by mamorani
Sun Mar 14, 2021 9:43 pm
The Deserializer block requires output vector size to be integer multiple of input vector size.

Last post by mamorani « Sun Mar 14, 2021 9:42 pm

by mamorani » Sun Mar 14, 2021 9:42 pm

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Last post by mamorani
Sun Mar 14, 2021 9:42 pm
The count direction port is redundant when counter size is 1 bit. Use of the port may result in an unused signal or port

Last post by mamorani « Sun Mar 14, 2021 9:42 pm

by mamorani » Sun Mar 14, 2021 9:42 pm

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Last post by mamorani
Sun Mar 14, 2021 9:42 pm
Unknown property name in implementation parameters

Last post by mamorani « Sun Mar 14, 2021 9:41 pm

by mamorani » Sun Mar 14, 2021 9:41 pm

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Last post by mamorani
Sun Mar 14, 2021 9:41 pm
The step value cannot be represented by using the selected data type. HDL Counter uses the absolute value of the step va

Last post by mamorani « Sun Mar 14, 2021 9:41 pm

by mamorani » Sun Mar 14, 2021 9:41 pm

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Last post by mamorani
Sun Mar 14, 2021 9:41 pm
Word length must be 2 or more for a signed data type.

Last post by mamorani « Sun Mar 14, 2021 9:40 pm

by mamorani » Sun Mar 14, 2021 9:40 pm

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Last post by mamorani
Sun Mar 14, 2021 9:40 pm
Unhandled mixed double, single, and non-real datatypes at ports of block.

Last post by mamorani « Sun Mar 14, 2021 9:40 pm

by mamorani » Sun Mar 14, 2021 9:40 pm

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Last post by mamorani
Sun Mar 14, 2021 9:40 pm
All parameters of the HDL Counter block must be real, numeric scalars

Last post by mamorani « Sun Mar 14, 2021 9:40 pm

by mamorani » Sun Mar 14, 2021 9:40 pm

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Last post by mamorani
Sun Mar 14, 2021 9:40 pm
Initial value" and "Count to value" cannot be the same

Last post by mamorani « Sun Mar 14, 2021 9:39 pm

by mamorani » Sun Mar 14, 2021 9:39 pm

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Last post by mamorani
Sun Mar 14, 2021 9:39 pm
Fraction length must be less than word length for a signed data type.

Last post by mamorani « Sun Mar 14, 2021 9:39 pm

by mamorani » Sun Mar 14, 2021 9:39 pm

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Last post by mamorani
Sun Mar 14, 2021 9:39 pm
HDL Counter block with ''Counter type'' parameter set to ''Modulo'' does not support fractional values

Last post by mamorani « Sun Mar 14, 2021 9:39 pm

by mamorani » Sun Mar 14, 2021 9:39 pm

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Last post by mamorani
Sun Mar 14, 2021 9:39 pm
Fraction length must be a positive integer or zero

Last post by mamorani « Sun Mar 14, 2021 9:39 pm

by mamorani » Sun Mar 14, 2021 9:39 pm

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Last post by mamorani
Sun Mar 14, 2021 9:39 pm
cannot be represented with the selected fraction length

Last post by mamorani « Sun Mar 14, 2021 9:38 pm

by mamorani » Sun Mar 14, 2021 9:38 pm

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Last post by mamorani
Sun Mar 14, 2021 9:38 pm
HDL Counter block requires current model''s parameters ''DataTypeOverride'' to be ''UseLocalSettings'', ''Off', or ''For

Last post by mamorani « Sun Mar 14, 2021 9:38 pm

by mamorani » Sun Mar 14, 2021 9:38 pm

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Last post by mamorani
Sun Mar 14, 2021 9:38 pm

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