is used by simulation and requires reset be asserted for at least 100 ns. However, the current test bench settings only
Posted: Sun Mar 14, 2021 9:02 pm
is used by simulation and requires reset be asserted for at least 100 ns. However, the current test bench settings only assert reset for ns, i.e. (ClockHighTime + ClockLowTime) * ResetLength. It is recommended to increase ResetLength to extend the reset time.
hdlshared
hdlshared