Identifiers and names should follow recommended naming convention (1.A.A.2), and keywords in Verilog-HDL(IEEE1364), Syst
Posted: Fri Mar 12, 2021 11:18 pm
Identifiers and names should follow recommended naming convention (1.A.A.2), and keywords in Verilog-HDL(IEEE1364), SystemVerilog(v3.1a), and keywords in VHDL(IEEE1076.X) must not be used
Standard
Standard