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Port of model is a vector or matrix port, which must be scalarized when on a Model Reference interface for VHDL code ge

Posted: Fri Mar 12, 2021 2:24 pm
by mamorani
Port of model is a vector or matrix port, which must be scalarized when on a Model Reference interface for VHDL code generation. Set the ''Scalarize ports'' HDL coding style parameter to ''on'' to generate code for this model.

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