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Assertion blocks with Architecture set to Assertion in the mode can trigger unexpected RTL simulation failures due to i

Posted: Fri Mar 12, 2021 11:31 am
by mamorani
Assertion blocks with Architecture set to Assertion in the mode can trigger unexpected RTL simulation failures due to initial value propagation through no-reset delay blocks. To avoid these failures, disable code generation options such as streaming, distributed pipelining, and resource sharing, or set the Assertion block architecture to NoHDL.

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