Rate mismatch at the output of Rate Transition block connected to port Change the output sample time of ' to match the
Posted: Wed Mar 10, 2021 9:45 pm
Rate mismatch at the output of Rate Transition block connected to port Change the output sample time of ' to match the output rate for all other Serializer1D blocks connected to AXI4-Stream interface ports
hdlstreaming
hdlstreaming