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The delay block with vector input cannot be optimized, because the delay length is greater than one, and the initial con

Last post by mamorani « Wed Mar 10, 2021 11:50 pm

by mamorani » Wed Mar 10, 2021 11:50 pm

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Last post by mamorani
Wed Mar 10, 2021 11:50 pm
The enabled or resettable delay block cannot be optimized, because the delay length is greater than one, and the initial

Last post by mamorani « Wed Mar 10, 2021 11:50 pm

by mamorani » Wed Mar 10, 2021 11:50 pm

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180 Views

Last post by mamorani
Wed Mar 10, 2021 11:50 pm
The delay block cannot be optimized because the delay length is larger than

Last post by mamorani « Wed Mar 10, 2021 11:50 pm

by mamorani » Wed Mar 10, 2021 11:50 pm

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Last post by mamorani
Wed Mar 10, 2021 11:50 pm
hdlcoder.optimizeDesign cannot proceed, because the original design fails to do delay balancing:

Last post by mamorani « Wed Mar 10, 2021 11:49 pm

by mamorani » Wed Mar 10, 2021 11:49 pm

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Last post by mamorani
Wed Mar 10, 2021 11:49 pm
This signal is in an atomic subsystem instantiated multiple times

Last post by mamorani « Wed Mar 10, 2021 11:49 pm

by mamorani » Wed Mar 10, 2021 11:49 pm

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Last post by mamorani
Wed Mar 10, 2021 11:49 pm
All this signal's receivers are either delays or top level output ports

Last post by mamorani « Wed Mar 10, 2021 11:49 pm

by mamorani » Wed Mar 10, 2021 11:49 pm

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Last post by mamorani
Wed Mar 10, 2021 11:49 pm
This signal's driver is either a delay or a top level input port

Last post by mamorani « Wed Mar 10, 2021 11:48 pm

by mamorani » Wed Mar 10, 2021 11:48 pm

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Last post by mamorani
Wed Mar 10, 2021 11:48 pm
Pipelines requested exceed clock-rate pipelining budget. To raise the budget, increase OverSampling.

Last post by mamorani « Wed Mar 10, 2021 11:48 pm

by mamorani » Wed Mar 10, 2021 11:48 pm

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154 Views

Last post by mamorani
Wed Mar 10, 2021 11:48 pm
Because sets on ConstrainedOutputPipeline, hdlcoder.optimizeDesign may result in sub-optimal result. It is recommended

Last post by mamorani « Wed Mar 10, 2021 11:48 pm

by mamorani » Wed Mar 10, 2021 11:48 pm

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Last post by mamorani
Wed Mar 10, 2021 11:48 pm
Cannot regenerate code with saved data, because either the model or HDL Coder has changed.

Last post by mamorani « Wed Mar 10, 2021 11:47 pm

by mamorani » Wed Mar 10, 2021 11:47 pm

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170 Views

Last post by mamorani
Wed Mar 10, 2021 11:47 pm
Cannot restore working directory from because it does not contain The resumption directory may have been corrupted. Ple

Last post by mamorani « Wed Mar 10, 2021 11:47 pm

by mamorani » Wed Mar 10, 2021 11:47 pm

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161 Views

Last post by mamorani
Wed Mar 10, 2021 11:47 pm
Cannot restore from because HDL Coder version has changed.\nCurrent version:\n The resumption point was generated by:

Last post by mamorani « Wed Mar 10, 2021 11:46 pm

by mamorani » Wed Mar 10, 2021 11:46 pm

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160 Views

Last post by mamorani
Wed Mar 10, 2021 11:46 pm
Delay cannot be inserted in this signal, because

Last post by mamorani « Wed Mar 10, 2021 11:46 pm

by mamorani » Wed Mar 10, 2021 11:46 pm

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Last post by mamorani
Wed Mar 10, 2021 11:46 pm
The following critical path data may not be accurate because of the following reasons

Last post by mamorani « Wed Mar 10, 2021 11:45 pm

by mamorani » Wed Mar 10, 2021 11:45 pm

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Last post by mamorani
Wed Mar 10, 2021 11:45 pm
We found a fake combinational loop in your design while working on High-level critical path. Turning off Critical path e

Last post by mamorani « Wed Mar 10, 2021 11:45 pm

by mamorani » Wed Mar 10, 2021 11:45 pm

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147 Views

Last post by mamorani
Wed Mar 10, 2021 11:45 pm
hdlcoder.optimizeDesign does not support designs containing subsystems of BlackBox architecture. The following subsystem

Last post by mamorani « Wed Mar 10, 2021 11:45 pm

by mamorani » Wed Mar 10, 2021 11:45 pm

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148 Views

Last post by mamorani
Wed Mar 10, 2021 11:45 pm
The adaptive pipelining setting is disabled, but the block introduced adaptive pipelines. The chosen settings for this

Last post by mamorani « Wed Mar 10, 2021 11:44 pm

by mamorani » Wed Mar 10, 2021 11:44 pm

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146 Views

Last post by mamorani
Wed Mar 10, 2021 11:44 pm
Block ' does not support cascade architecture for matrix inputs. To generate HDL code, switch to Tree or Linear archite

Last post by mamorani « Wed Mar 10, 2021 11:42 pm

by mamorani » Wed Mar 10, 2021 11:42 pm

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214 Views

Last post by mamorani
Wed Mar 10, 2021 11:42 pm
Block does not support matrix types on its ports for HDL code generation.

Last post by mamorani « Wed Mar 10, 2021 11:41 pm

by mamorani » Wed Mar 10, 2021 11:41 pm

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181 Views

Last post by mamorani
Wed Mar 10, 2021 11:41 pm
Matrix support is limited to a maximum of 2 dimensions for HDL code generation

Last post by mamorani « Wed Mar 10, 2021 11:41 pm

by mamorani » Wed Mar 10, 2021 11:41 pm

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151 Views

Last post by mamorani
Wed Mar 10, 2021 11:41 pm
Top level record port ' ' contains field ' of matrix type, which is not supported for HDL code generation.<

Last post by mamorani « Wed Mar 10, 2021 11:40 pm

by mamorani » Wed Mar 10, 2021 11:40 pm

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151 Views

Last post by mamorani
Wed Mar 10, 2021 11:40 pm
Matrix multiplication is only supported for 2 inputs

Last post by mamorani « Wed Mar 10, 2021 11:40 pm

by mamorani » Wed Mar 10, 2021 11:40 pm

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152 Views

Last post by mamorani
Wed Mar 10, 2021 11:40 pm
Matrix addition is only supported for 2 inputs.

Last post by mamorani « Wed Mar 10, 2021 11:39 pm

by mamorani » Wed Mar 10, 2021 11:39 pm

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173 Views

Last post by mamorani
Wed Mar 10, 2021 11:39 pm
Constant block ''Logic Value'' HDL architecture does not support matrix typed signals

Last post by mamorani « Wed Mar 10, 2021 11:39 pm

by mamorani » Wed Mar 10, 2021 11:39 pm

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143 Views

Last post by mamorani
Wed Mar 10, 2021 11:39 pm
Matrix signals are not supported by Delay block in frame mode.

Last post by mamorani « Wed Mar 10, 2021 11:39 pm

by mamorani » Wed Mar 10, 2021 11:39 pm

0 Replies

157 Views

Last post by mamorani
Wed Mar 10, 2021 11:39 pm

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