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Subsystems being shared contain tunable mask parameters and 'Generate parameterized HDL code from masked subsystem' is t

Last post by mamorani « Thu Mar 11, 2021 3:56 pm

by mamorani » Thu Mar 11, 2021 3:56 pm

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Last post by mamorani
Thu Mar 11, 2021 3:56 pm
The latency budget is too small to perform streaming for pipelined floating point operations. Consider increasing the Ov

Last post by mamorani « Thu Mar 11, 2021 3:54 pm

by mamorani » Thu Mar 11, 2021 3:54 pm

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Last post by mamorani
Thu Mar 11, 2021 3:54 pm
All blocks inside sharable subsystems must have their \'sample time\' set to -1

Last post by mamorani « Thu Mar 11, 2021 3:54 pm

by mamorani » Thu Mar 11, 2021 3:54 pm

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Last post by mamorani
Thu Mar 11, 2021 3:54 pm
Delay introduced in feedback loop cannot be path balanced

Last post by mamorani « Thu Mar 11, 2021 3:50 pm

by mamorani » Thu Mar 11, 2021 3:50 pm

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Last post by mamorani
Thu Mar 11, 2021 3:50 pm
Sharing of clock-rate pipelined subsystems is disallowed

Last post by mamorani « Thu Mar 11, 2021 3:47 pm

by mamorani » Thu Mar 11, 2021 3:47 pm

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Last post by mamorani
Thu Mar 11, 2021 3:47 pm
Clock-rate pipelining was applied in a feedback loop and introduced a sample step delay. Consider increasing the Oversam

Last post by mamorani « Thu Mar 11, 2021 3:44 pm

by mamorani » Thu Mar 11, 2021 3:44 pm

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245 Views

Last post by mamorani
Thu Mar 11, 2021 3:44 pm
All instances of a re-used must have their BalanceDelays setting resolve to the same value. Found at least one re-used i

Last post by mamorani « Thu Mar 11, 2021 3:43 pm

by mamorani » Thu Mar 11, 2021 3:43 pm

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258 Views

Last post by mamorani
Thu Mar 11, 2021 3:43 pm
Atomic subsystem inhibits delay balancing. Consider making it non-atomic.

Last post by mamorani « Thu Mar 11, 2021 3:41 pm

by mamorani » Thu Mar 11, 2021 3:41 pm

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264 Views

Last post by mamorani
Thu Mar 11, 2021 3:41 pm
The sample time ratio of the slowest rate to the fastest (base) rate is too large

Last post by mamorani « Thu Mar 11, 2021 3:41 pm

by mamorani » Thu Mar 11, 2021 3:41 pm

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250 Views

Last post by mamorani
Thu Mar 11, 2021 3:41 pm
Target Frequency must be 0 for Microsemi Libero SoC.

Last post by mamorani « Thu Mar 11, 2021 3:39 pm

by mamorani » Thu Mar 11, 2021 3:39 pm

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257 Views

Last post by mamorani
Thu Mar 11, 2021 3:39 pm
Delay balancing failed because pipeline delays were added inside feedback loops. For all blocks inside the feedback loop

Last post by mamorani « Thu Mar 11, 2021 3:33 pm

by mamorani » Thu Mar 11, 2021 3:33 pm

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371 Views

Last post by mamorani
Thu Mar 11, 2021 3:33 pm
Design contains no native floating-point mathematical operators

Last post by mamorani « Thu Mar 11, 2021 3:31 pm

by mamorani » Thu Mar 11, 2021 3:31 pm

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282 Views

Last post by mamorani
Thu Mar 11, 2021 3:31 pm
No opportunities were found to flatten the Hierarchy

Last post by mamorani « Thu Mar 11, 2021 3:30 pm

by mamorani » Thu Mar 11, 2021 3:30 pm

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277 Views

Last post by mamorani
Thu Mar 11, 2021 3:30 pm
Note: This report does not account for the device-specific resources, which are exclusively captured in the Device-speci

Last post by mamorani « Thu Mar 11, 2021 3:29 pm

by mamorani » Thu Mar 11, 2021 3:29 pm

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273 Views

Last post by mamorani
Thu Mar 11, 2021 3:29 pm
Note: Subsystem marked with (*) indicates that even though hierarchy flattening failed, the HDL Code is inlined in a sin

Last post by mamorani « Thu Mar 11, 2021 3:27 pm

by mamorani » Thu Mar 11, 2021 3:27 pm

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289 Views

Last post by mamorani
Thu Mar 11, 2021 3:27 pm
No subsystems found with the HDL block property ''FlattenHierarchy'' turned ''on''

Last post by mamorani « Thu Mar 11, 2021 3:21 pm

by mamorani » Thu Mar 11, 2021 3:21 pm

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254 Views

Last post by mamorani
Thu Mar 11, 2021 3:21 pm
Delay balancing failed because pipeline delays were added inside feedback loops. For all blocks inside the feedback loop

Last post by mamorani « Thu Mar 11, 2021 3:20 pm

by mamorani » Thu Mar 11, 2021 3:20 pm

0 Replies

270 Views

Last post by mamorani
Thu Mar 11, 2021 3:20 pm
Uncharacterized blocks were detected in the design. In the presence of uncharacterized blocks, the latency value estimat

Last post by mamorani « Thu Mar 11, 2021 3:19 pm

by mamorani » Thu Mar 11, 2021 3:19 pm

0 Replies

248 Views

Last post by mamorani
Thu Mar 11, 2021 3:19 pm
Loops were detected in the design. In the presence of loops, the latency value is an estimate of the longest path that i

Last post by mamorani « Thu Mar 11, 2021 3:19 pm

by mamorani » Thu Mar 11, 2021 3:19 pm

0 Replies

258 Views

Last post by mamorani
Thu Mar 11, 2021 3:19 pm
No valid paths were found from any input to any output of the subsystem.

Last post by mamorani « Thu Mar 11, 2021 3:18 pm

by mamorani » Thu Mar 11, 2021 3:18 pm

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240 Views

Last post by mamorani
Thu Mar 11, 2021 3:18 pm
The blocks listed are not supported for 'Code Obfuscation'. The generated HDL code for the corresponding hierarchy is no

Last post by mamorani « Thu Mar 11, 2021 3:18 pm

by mamorani » Thu Mar 11, 2021 3:18 pm

0 Replies

257 Views

Last post by mamorani
Thu Mar 11, 2021 3:18 pm
The specified configuration parameters listed are incompatible with 'Code Obfuscation' feature and have been ignored

Last post by mamorani « Thu Mar 11, 2021 3:17 pm

by mamorani » Thu Mar 11, 2021 3:17 pm

0 Replies

267 Views

Last post by mamorani
Thu Mar 11, 2021 3:17 pm
CDATA[ For more information, refer to the <a href="matlab:helpview(fullfile(docroot, 'hdlcoder', 'helptargets.map'),'msg

Last post by mamorani « Thu Mar 11, 2021 3:15 pm

by mamorani » Thu Mar 11, 2021 3:15 pm

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275 Views

Last post by mamorani
Thu Mar 11, 2021 3:15 pm
These reusable atomic subsystems are identical and the following section applies to all identical instances. Only one of

Last post by mamorani « Thu Mar 11, 2021 3:14 pm

by mamorani » Thu Mar 11, 2021 3:14 pm

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256 Views

Last post by mamorani
Thu Mar 11, 2021 3:14 pm
High-level Native Floating-point Resource Utilization report for

Last post by mamorani « Thu Mar 11, 2021 3:14 pm

by mamorani » Thu Mar 11, 2021 3:14 pm

0 Replies

263 Views

Last post by mamorani
Thu Mar 11, 2021 3:14 pm

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