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Unsupported global variable used in your design function. HDL Coder cannot continue code generation.

Last post by mamorani « Fri Mar 12, 2021 10:07 am

by mamorani » Fri Mar 12, 2021 10:07 am

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139 Views

Last post by mamorani
Fri Mar 12, 2021 10:07 am
Found unsupported division expression for HDL code generation; Signed input data type is not supported for division wit

Last post by mamorani « Fri Mar 12, 2021 10:07 am

by mamorani » Fri Mar 12, 2021 10:07 am

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151 Views

Last post by mamorani
Fri Mar 12, 2021 10:07 am
A cast between fixpt and floating point type is not supported, at

Last post by mamorani « Fri Mar 12, 2021 10:06 am

by mamorani » Fri Mar 12, 2021 10:06 am

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163 Views

Last post by mamorani
Fri Mar 12, 2021 10:06 am
A cast to or from an enumerated type is not supported, at

Last post by mamorani « Fri Mar 12, 2021 10:06 am

by mamorani » Fri Mar 12, 2021 10:06 am

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151 Views

Last post by mamorani
Fri Mar 12, 2021 10:06 am
When comparing values of enumerated type, the types must be identical, at

Last post by mamorani « Fri Mar 12, 2021 10:06 am

by mamorani » Fri Mar 12, 2021 10:06 am

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143 Views

Last post by mamorani
Fri Mar 12, 2021 10:06 am
A switch statement must have either none or all of its case choices be of enumerated type, at

Last post by mamorani « Fri Mar 12, 2021 10:05 am

by mamorani » Fri Mar 12, 2021 10:05 am

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121 Views

Last post by mamorani
Fri Mar 12, 2021 10:05 am
When assigning an enumerated type, the source and destination types must be identical, at

Last post by mamorani « Fri Mar 12, 2021 10:05 am

by mamorani » Fri Mar 12, 2021 10:05 am

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143 Views

Last post by mamorani
Fri Mar 12, 2021 10:05 am
HDL code generation does not support arithmetic on enumerated types, at

Last post by mamorani « Fri Mar 12, 2021 10:05 am

by mamorani » Fri Mar 12, 2021 10:05 am

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113 Views

Last post by mamorani
Fri Mar 12, 2021 10:05 am
Enumerated name introduces conflicting values. Please use unique enum type name and enum value pairs for Verilog code

Last post by mamorani « Fri Mar 12, 2021 10:04 am

by mamorani » Fri Mar 12, 2021 10:04 am

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132 Views

Last post by mamorani
Fri Mar 12, 2021 10:04 am
Enumerated name conflicts with the signal name . This can lead to non synthesizable code.

Last post by mamorani « Fri Mar 12, 2021 10:04 am

by mamorani » Fri Mar 12, 2021 10:04 am

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111 Views

Last post by mamorani
Fri Mar 12, 2021 10:04 am
Enumerated name ' ' is present in types and ' . Use unique enum type names for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 10:03 am

by mamorani » Fri Mar 12, 2021 10:03 am

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175 Views

Last post by mamorani
Fri Mar 12, 2021 10:03 am
The enumeration type contains an element with the enumeration identifier ' , which is either a language keyword, or is

Last post by mamorani « Fri Mar 12, 2021 10:03 am

by mamorani » Fri Mar 12, 2021 10:03 am

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188 Views

Last post by mamorani
Fri Mar 12, 2021 10:03 am
Altera DSPBA subsystem entity causes name conflict. Please rename it.

Last post by mamorani « Fri Mar 12, 2021 10:02 am

by mamorani » Fri Mar 12, 2021 10:02 am

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134 Views

Last post by mamorani
Fri Mar 12, 2021 10:02 am
cannot be represented with the selected fraction length

Last post by mamorani « Fri Mar 12, 2021 10:02 am

by mamorani » Fri Mar 12, 2021 10:02 am

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134 Views

Last post by mamorani
Fri Mar 12, 2021 10:02 am
There are no models open with the name to apply the control file

Last post by mamorani « Fri Mar 12, 2021 10:02 am

by mamorani » Fri Mar 12, 2021 10:02 am

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157 Views

Last post by mamorani
Fri Mar 12, 2021 10:02 am
The periodic sample time is not allowed because the ratio of this sample time over the HDL DUT base rate is greater t

Last post by mamorani « Fri Mar 12, 2021 10:01 am

by mamorani » Fri Mar 12, 2021 10:01 am

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137 Views

Last post by mamorani
Fri Mar 12, 2021 10:01 am
The following parameters are transient and cannot be set with hdlset_param:

Last post by mamorani « Fri Mar 12, 2021 10:01 am

by mamorani » Fri Mar 12, 2021 10:01 am

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140 Views

Last post by mamorani
Fri Mar 12, 2021 10:01 am
Setting Simulink binary-point to maximum value of 1024; HDL results may not match

Last post by mamorani « Fri Mar 12, 2021 10:01 am

by mamorani » Fri Mar 12, 2021 10:01 am

0 Replies

159 Views

Last post by mamorani
Fri Mar 12, 2021 10:01 am
Cannot find required information -- please make sure the block is in a model, not a library.

Last post by mamorani « Fri Mar 12, 2021 10:00 am

by mamorani » Fri Mar 12, 2021 10:00 am

0 Replies

148 Views

Last post by mamorani
Fri Mar 12, 2021 10:00 am
Invalid ''Architecture'' parameter specified for the block\nValid Architecture names are

Last post by mamorani « Fri Mar 12, 2021 10:00 am

by mamorani » Fri Mar 12, 2021 10:00 am

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144 Views

Last post by mamorani
Fri Mar 12, 2021 10:00 am
Critical Path Estimation doesn't support Float/Double types. Run diagnostics script for details.

Last post by mamorani « Fri Mar 12, 2021 10:00 am

by mamorani » Fri Mar 12, 2021 10:00 am

0 Replies

154 Views

Last post by mamorani
Fri Mar 12, 2021 10:00 am
Model Reference as top-level subsystem is not support for traceability report generation

Last post by mamorani « Fri Mar 12, 2021 9:59 am

by mamorani » Fri Mar 12, 2021 9:59 am

0 Replies

127 Views

Last post by mamorani
Fri Mar 12, 2021 9:59 am
Floating Point Target IP generation failed with the error message:

Last post by mamorani « Fri Mar 12, 2021 9:59 am

by mamorani » Fri Mar 12, 2021 9:59 am

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162 Views

Last post by mamorani
Fri Mar 12, 2021 9:59 am
Trigger as clock mode requires synchronization registers for each input data signal to a triggered subsystem. Subsystem

Last post by mamorani « Fri Mar 12, 2021 9:59 am

by mamorani » Fri Mar 12, 2021 9:59 am

0 Replies

154 Views

Last post by mamorani
Fri Mar 12, 2021 9:59 am
The block contains unsupported struct expressions. HDL code generation cannot proceed because of the unsupported constr

Last post by mamorani « Fri Mar 12, 2021 9:58 am

by mamorani » Fri Mar 12, 2021 9:58 am

0 Replies

141 Views

Last post by mamorani
Fri Mar 12, 2021 9:58 am

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