Signal Processing

New Topic

3049 topics

Page 77 of 122
- Jump to page:
Previous
1
…
75
76
77
78
79
…
122
Next

Topics

Replies

Views

Last post

The UseMatrixTypesInHDL option is incompatible with the InstantiateFunctions/'Generate instantiable code for functions'

Last post by mamorani « Fri Mar 12, 2021 10:56 am

by mamorani » Fri Mar 12, 2021 10:56 am

0 Replies

207 Views

Last post by mamorani
Fri Mar 12, 2021 10:56 am
Unsupported variable ', of struct type found. Continuing with UseMatrixTypesInHDL disabledbled.

Last post by mamorani « Fri Mar 12, 2021 10:56 am

by mamorani » Fri Mar 12, 2021 10:56 am

0 Replies

242 Views

Last post by mamorani
Fri Mar 12, 2021 10:56 am
UseMatrixTypesInHDL is only supported for 2-dimensional matrices. Variable, ' '', is a -dimensional matrix. Continuing

Last post by mamorani « Fri Mar 12, 2021 10:55 am

by mamorani » Fri Mar 12, 2021 10:55 am

0 Replies

239 Views

Last post by mamorani
Fri Mar 12, 2021 10:55 am
Unsupported loop bounds found. Continuing with UseMatrixTypesInHDL disabled.

Last post by mamorani « Fri Mar 12, 2021 10:55 am

by mamorani » Fri Mar 12, 2021 10:55 am

0 Replies

342 Views

Last post by mamorani
Fri Mar 12, 2021 10:55 am
Loop streaming failed because a state variable, , has non-zero initial value and is being updated inside the loop

Last post by mamorani « Fri Mar 12, 2021 10:55 am

by mamorani » Fri Mar 12, 2021 10:55 am

0 Replies

193 Views

Last post by mamorani
Fri Mar 12, 2021 10:55 am
Could not apply coder.hdl.loopspec pragma with the 'stream' option. This could be because the 'stream' option was applie

Last post by mamorani « Fri Mar 12, 2021 10:54 am

by mamorani » Fri Mar 12, 2021 10:54 am

0 Replies

415 Views

Last post by mamorani
Fri Mar 12, 2021 10:54 am
The streaming factor, , provided to the coder.hdl.loopspec pragma does not evenly divide the number of loop iterations

Last post by mamorani « Fri Mar 12, 2021 10:54 am

by mamorani » Fri Mar 12, 2021 10:54 am

0 Replies

213 Views

Last post by mamorani
Fri Mar 12, 2021 10:54 am
No unrolling factor specified for coder.hdl.loopspec pragma. Using default unrolling factor of

Last post by mamorani « Fri Mar 12, 2021 10:53 am

by mamorani » Fri Mar 12, 2021 10:53 am

0 Replies

209 Views

Last post by mamorani
Fri Mar 12, 2021 10:53 am
Invalid streaming factor, specified for coder.hdl.loopspec pragma. Streaming factor must be greater than 0 and less tha

Last post by mamorani « Fri Mar 12, 2021 10:53 am

by mamorani » Fri Mar 12, 2021 10:53 am

0 Replies

201 Views

Last post by mamorani
Fri Mar 12, 2021 10:53 am
No streaming factor specified for coder.hdl.loopspec pragma. Using default streaming factor of

Last post by mamorani « Fri Mar 12, 2021 10:52 am

by mamorani » Fri Mar 12, 2021 10:52 am

0 Replies

194 Views

Last post by mamorani
Fri Mar 12, 2021 10:52 am
Found an unsupported unbounded loop structure. This loop may be user written or automatically generated due to the use o

Last post by mamorani « Fri Mar 12, 2021 10:52 am

by mamorani » Fri Mar 12, 2021 10:52 am

0 Replies

272 Views

Last post by mamorani
Fri Mar 12, 2021 10:52 am
IP Core Generation workflow does not support ''SynthesizeGeneratedCode'' and ''PlaceAndRoute'' options. Please use 'Crea

Last post by mamorani « Fri Mar 12, 2021 10:51 am

by mamorani » Fri Mar 12, 2021 10:51 am

0 Replies

280 Views

Last post by mamorani
Fri Mar 12, 2021 10:51 am
Delay balancing failed due to an artificial feedback loop. Consider disabling the 'Generate instantiable code for functi

Last post by mamorani « Fri Mar 12, 2021 10:51 am

by mamorani » Fri Mar 12, 2021 10:51 am

0 Replies

236 Views

Last post by mamorani
Fri Mar 12, 2021 10:51 am
To automatically open the conformance check report, select 'Check HDL conformance' report on GUI, or set CheckConforma

Last post by mamorani « Fri Mar 12, 2021 10:51 am

by mamorani » Fri Mar 12, 2021 10:51 am

0 Replies

216 Views

Last post by mamorani
Fri Mar 12, 2021 10:51 am
HDL Conformance check complete with errors, warnings, and messages.

Last post by mamorani « Fri Mar 12, 2021 10:50 am

by mamorani » Fri Mar 12, 2021 10:50 am

0 Replies

332 Views

Last post by mamorani
Fri Mar 12, 2021 10:50 am
Xilinx system generator subsystem entity causes name conflict. This must be renamed.

Last post by mamorani « Fri Mar 12, 2021 10:49 am

by mamorani » Fri Mar 12, 2021 10:49 am

0 Replies

250 Views

Last post by mamorani
Fri Mar 12, 2021 10:49 am
Signal with unsupported word length of is detected at the input of block HDL code generation for block with fixed-poi

Last post by mamorani « Fri Mar 12, 2021 10:49 am

by mamorani » Fri Mar 12, 2021 10:49 am

0 Replies

257 Views

Last post by mamorani
Fri Mar 12, 2021 10:49 am
Setting Simulink word length to maximum value of 128; HDL results may not match

Last post by mamorani « Fri Mar 12, 2021 10:48 am

by mamorani » Fri Mar 12, 2021 10:48 am

0 Replies

220 Views

Last post by mamorani
Fri Mar 12, 2021 10:48 am
Generating HDL code for a variant subsystem ' in the model not supported.

Last post by mamorani « Fri Mar 12, 2021 10:47 am

by mamorani » Fri Mar 12, 2021 10:47 am

0 Replies

270 Views

Last post by mamorani
Fri Mar 12, 2021 10:47 am
Signal with unsupported word length of is detected at the input of block HDL code generation for block with fixed-poin

Last post by mamorani « Fri Mar 12, 2021 10:47 am

by mamorani » Fri Mar 12, 2021 10:47 am

0 Replies

202 Views

Last post by mamorani
Fri Mar 12, 2021 10:47 am
Slope and Bias data-types not supported for HDL Code generation

Last post by mamorani « Fri Mar 12, 2021 10:46 am

by mamorani » Fri Mar 12, 2021 10:46 am

0 Replies

203 Views

Last post by mamorani
Fri Mar 12, 2021 10:46 am
Unconnected bidirectional port in component of network found.

Last post by mamorani « Fri Mar 12, 2021 10:46 am

by mamorani » Fri Mar 12, 2021 10:46 am

0 Replies

209 Views

Last post by mamorani
Fri Mar 12, 2021 10:46 am
The output sample rate must be an integer ratio of the input sample rate.

Last post by mamorani « Fri Mar 12, 2021 10:45 am

by mamorani » Fri Mar 12, 2021 10:45 am

0 Replies

207 Views

Last post by mamorani
Fri Mar 12, 2021 10:45 am
The output sample rate must be an integer ratio of the input sample rate.

Last post by mamorani « Fri Mar 12, 2021 10:43 am

by mamorani » Fri Mar 12, 2021 10:43 am

0 Replies

200 Views

Last post by mamorani
Fri Mar 12, 2021 10:43 am
The combination of coder options chosen require an overclocking factor of x, which violates the MaxOversampling

Last post by mamorani « Fri Mar 12, 2021 10:26 am

by mamorani » Fri Mar 12, 2021 10:26 am

0 Replies

406 Views

Last post by mamorani
Fri Mar 12, 2021 10:26 am

New Topic

3049 topics

Page 77 of 122
- Jump to page:
Previous
1
…
75
76
77
78
79
…
122
Next

Return to Board Index

Who is online

Users browsing this forum: No registered users and 1 guest

Forum permissions

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum