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Continuous-time mode not supported for HDL Code generation

Last post by mamorani « Fri Mar 12, 2021 2:45 pm

by mamorani » Fri Mar 12, 2021 2:45 pm

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144 Views

Last post by mamorani
Fri Mar 12, 2021 2:45 pm
Input types must not be Double when clamping Anti-windup mode is used for HDL Code generation.

Last post by mamorani « Fri Mar 12, 2021 2:44 pm

by mamorani » Fri Mar 12, 2021 2:44 pm

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153 Views

Last post by mamorani
Fri Mar 12, 2021 2:44 pm
Initialize output(Y) must be ''Initialize using input port <Y0>'' in assignment blocks for HDL code generation

Last post by mamorani « Fri Mar 12, 2021 2:44 pm

by mamorani » Fri Mar 12, 2021 2:44 pm

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155 Views

Last post by mamorani
Fri Mar 12, 2021 2:44 pm
Output cannot be of unsigned type for target-specific code generation.

Last post by mamorani « Fri Mar 12, 2021 2:43 pm

by mamorani » Fri Mar 12, 2021 2:43 pm

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140 Views

Last post by mamorani
Fri Mar 12, 2021 2:43 pm
The total number of inputs for this block cannot be more than 2 for target-specific code generation

Last post by mamorani « Fri Mar 12, 2021 2:43 pm

by mamorani » Fri Mar 12, 2021 2:43 pm

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143 Views

Last post by mamorani
Fri Mar 12, 2021 2:43 pm
Only Tree Architecture is supported for target-specific code generation

Last post by mamorani « Fri Mar 12, 2021 2:43 pm

by mamorani » Fri Mar 12, 2021 2:43 pm

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150 Views

Last post by mamorani
Fri Mar 12, 2021 2:43 pm
Output data-type must be ''boolean'' for target-specific code generation

Last post by mamorani « Fri Mar 12, 2021 2:42 pm

by mamorani » Fri Mar 12, 2021 2:42 pm

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150 Views

Last post by mamorani
Fri Mar 12, 2021 2:42 pm
The block is inside an Observer, which is not supported by HDL coder

Last post by mamorani « Fri Mar 12, 2021 2:42 pm

by mamorani » Fri Mar 12, 2021 2:42 pm

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158 Views

Last post by mamorani
Fri Mar 12, 2021 2:42 pm
The model ' contains Observers, which are not supported by HDL coder. Please remove or comment out all Observers in the

Last post by mamorani « Fri Mar 12, 2021 2:41 pm

by mamorani » Fri Mar 12, 2021 2:41 pm

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157 Views

Last post by mamorani
Fri Mar 12, 2021 2:41 pm
After HDL code generation, block can have numeric differences when compared to the Simulink model. For details, view t

Last post by mamorani « Fri Mar 12, 2021 2:41 pm

by mamorani » Fri Mar 12, 2021 2:41 pm

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184 Views

Last post by mamorani
Fri Mar 12, 2021 2:41 pm
When the code generation subsystem is not at the top level of a model, the subsystem name can not be identical to the mo

Last post by mamorani « Fri Mar 12, 2021 2:40 pm

by mamorani » Fri Mar 12, 2021 2:40 pm

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154 Views

Last post by mamorani
Fri Mar 12, 2021 2:40 pm
Setting non-default accumulator data type on a ''Sum'' block inhibits pipelining optimizations. If you intend to pipelin

Last post by mamorani « Fri Mar 12, 2021 2:40 pm

by mamorani » Fri Mar 12, 2021 2:40 pm

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153 Views

Last post by mamorani
Fri Mar 12, 2021 2:40 pm
When MinimizeGlobalResets is enabled and ''NoResetInitializationMode'' is set to ''Script'', HDL Coder will only generat

Last post by mamorani « Fri Mar 12, 2021 2:40 pm

by mamorani » Fri Mar 12, 2021 2:40 pm

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147 Views

Last post by mamorani
Fri Mar 12, 2021 2:40 pm
Cascade implementation doesn''t support more than one input port for

Last post by mamorani « Fri Mar 12, 2021 2:39 pm

by mamorani » Fri Mar 12, 2021 2:39 pm

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142 Views

Last post by mamorani
Fri Mar 12, 2021 2:39 pm
Model block is inside a triggered or enabled subsystem, and has been configured to generate HDL code for the nested mod

Last post by mamorani « Fri Mar 12, 2021 2:39 pm

by mamorani » Fri Mar 12, 2021 2:39 pm

0 Replies

270 Views

Last post by mamorani
Fri Mar 12, 2021 2:39 pm
The "Mux blocks used to create bus signals" option is required to be set to "error" in the Connectivity pane of the Diag

Last post by mamorani « Fri Mar 12, 2021 2:38 pm

by mamorani » Fri Mar 12, 2021 2:38 pm

0 Replies

259 Views

Last post by mamorani
Fri Mar 12, 2021 2:38 pm
The model has a ResetType setting that may be incompatible for DSP mapping in Xilinx boards. Set the ResetType model pro

Last post by mamorani « Fri Mar 12, 2021 2:38 pm

by mamorani » Fri Mar 12, 2021 2:38 pm

0 Replies

161 Views

Last post by mamorani
Fri Mar 12, 2021 2:38 pm
Illegal value, , for option PipelineDepth, pass a number or ''auto''. Assuming ''auto'

Last post by mamorani « Fri Mar 12, 2021 2:37 pm

by mamorani » Fri Mar 12, 2021 2:37 pm

0 Replies

155 Views

Last post by mamorani
Fri Mar 12, 2021 2:37 pm
Synthesis tool is either unspecified or not supported. Specify a supported synthesis tool to apply a target-specific Pip

Last post by mamorani « Fri Mar 12, 2021 2:33 pm

by mamorani » Fri Mar 12, 2021 2:33 pm

0 Replies

137 Views

Last post by mamorani
Fri Mar 12, 2021 2:33 pm
PipelineDepth option is not supported for blocks with floating-point inputs

Last post by mamorani « Fri Mar 12, 2021 2:33 pm

by mamorani » Fri Mar 12, 2021 2:33 pm

0 Replies

110 Views

Last post by mamorani
Fri Mar 12, 2021 2:33 pm
The model has a ResetType setting that may be incompatible for DSP mapping in Xilinx boards. Set the ResetType model pro

Last post by mamorani « Fri Mar 12, 2021 2:33 pm

by mamorani » Fri Mar 12, 2021 2:33 pm

0 Replies

129 Views

Last post by mamorani
Fri Mar 12, 2021 2:33 pm
Using the Streaming modes of the Multiply-Accumulate Block inside a Resettable subsystem is not supported for HDL code g

Last post by mamorani « Fri Mar 12, 2021 2:32 pm

by mamorani » Fri Mar 12, 2021 2:32 pm

0 Replies

138 Views

Last post by mamorani
Fri Mar 12, 2021 2:32 pm
Sample rate mismatch. To make sure that the signals driving the input ports of the Multiply-Accumulate block arrive at t

Last post by mamorani « Fri Mar 12, 2021 2:32 pm

by mamorani » Fri Mar 12, 2021 2:32 pm

0 Replies

164 Views

Last post by mamorani
Fri Mar 12, 2021 2:32 pm
The Number of Samples needs to be a positive value. Set the num_samples model property to a positive integer

Last post by mamorani « Fri Mar 12, 2021 2:32 pm

by mamorani » Fri Mar 12, 2021 2:32 pm

0 Replies

141 Views

Last post by mamorani
Fri Mar 12, 2021 2:32 pm
Synthesis tool is either unspecified or not supported.

Last post by mamorani « Fri Mar 12, 2021 2:31 pm

by mamorani » Fri Mar 12, 2021 2:31 pm

0 Replies

177 Views

Last post by mamorani
Fri Mar 12, 2021 2:31 pm

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