Signal Processing

New Topic

3049 topics

Page 55 of 122
- Jump to page:
Previous
1
…
53
54
55
56
57
…
122
Next

Topics

Replies

Views

Last post

For Zynq or Altera SoC reference design, the ''JTAG'' programming method may be deprecated in the future release, please

Last post by mamorani « Fri Mar 12, 2021 9:13 pm

by mamorani » Fri Mar 12, 2021 9:13 pm

0 Replies

132 Views

Last post by mamorani
Fri Mar 12, 2021 9:13 pm
The synthesis tool, , is not a valid choice for the FPGA Turnkey Workflow. Please select from ''Xilinx ISE'', or ''Alte

Last post by mamorani « Fri Mar 12, 2021 9:11 pm

by mamorani » Fri Mar 12, 2021 9:11 pm

0 Replies

120 Views

Last post by mamorani
Fri Mar 12, 2021 9:11 pm
The synthesis tool, , is not a valid choice for the FPGA Turnkey Workflow. Please select from ''Xilinx ISE'', or ''Alte

Last post by mamorani « Fri Mar 12, 2021 8:46 pm

by mamorani » Fri Mar 12, 2021 8:46 pm

0 Replies

156 Views

Last post by mamorani
Fri Mar 12, 2021 8:46 pm
Menu selection ''Export to script'' does not support leaving the synthesis tool as . Please select from ''Xilinx Vivado

Last post by mamorani « Fri Mar 12, 2021 8:45 pm

by mamorani » Fri Mar 12, 2021 8:45 pm

0 Replies

148 Views

Last post by mamorani
Fri Mar 12, 2021 8:45 pm
The synthesis tool, ' is not a valid choice. Please select from ''Xilinx Vivado'', ''Xilinx ISE'', ''Altera QUARTUS II'

Last post by mamorani « Fri Mar 12, 2021 8:45 pm

by mamorani » Fri Mar 12, 2021 8:45 pm

0 Replies

146 Views

Last post by mamorani
Fri Mar 12, 2021 8:45 pm
The simulator, is not a valid choice. Please select from ''Mentor Graphics ModelSim'',''Cadence Incisive'

Last post by mamorani « Fri Mar 12, 2021 8:44 pm

by mamorani » Fri Mar 12, 2021 8:44 pm

0 Replies

151 Views

Last post by mamorani
Fri Mar 12, 2021 8:44 pm
ReportTimingFailure must be an element of the hdlcoder.ReportTiming enumerated type: hdlcoder.ReportTiming.Error or hdlc

Last post by mamorani « Fri Mar 12, 2021 8:44 pm

by mamorani » Fri Mar 12, 2021 8:44 pm

0 Replies

152 Views

Last post by mamorani
Fri Mar 12, 2021 8:44 pm
The programming method is not a valid option for this reference design.

Last post by mamorani « Fri Mar 12, 2021 8:44 pm

by mamorani » Fri Mar 12, 2021 8:44 pm

0 Replies

150 Views

Last post by mamorani
Fri Mar 12, 2021 8:44 pm
ProgrammingMethod must be an element of the hdlcoder.ProgrammingMethod enumerated type: hdlcoder.ProgrammingMethod.JTAG,

Last post by mamorani « Fri Mar 12, 2021 8:43 pm

by mamorani » Fri Mar 12, 2021 8:43 pm

0 Replies

146 Views

Last post by mamorani
Fri Mar 12, 2021 8:43 pm
The source, , is not a valid choice. Please select from ''pre-route'',''post-route''

Last post by mamorani « Fri Mar 12, 2021 8:38 pm

by mamorani » Fri Mar 12, 2021 8:38 pm

0 Replies

165 Views

Last post by mamorani
Fri Mar 12, 2021 8:38 pm
The path number, , is not a valid choice. Please select from, 1,2,3.

Last post by mamorani « Fri Mar 12, 2021 8:38 pm

by mamorani » Fri Mar 12, 2021 8:38 pm

0 Replies

149 Views

Last post by mamorani
Fri Mar 12, 2021 8:38 pm
Invalid entry for parameter ''Objective''. The value entered must be an element of the hdlcoder.Objective enumerated typ

Last post by mamorani « Fri Mar 12, 2021 8:37 pm

by mamorani » Fri Mar 12, 2021 8:37 pm

0 Replies

156 Views

Last post by mamorani
Fri Mar 12, 2021 8:37 pm
Invalid entry for parameter ''TclFileForSynthesisBuild''. The value entered must be an element of the hdlcoder.BuildOpti

Last post by mamorani « Fri Mar 12, 2021 8:37 pm

by mamorani » Fri Mar 12, 2021 8:37 pm

0 Replies

153 Views

Last post by mamorani
Fri Mar 12, 2021 8:37 pm
Install Speedgoat Library and Speedgoat HDL Coder Integration Package to get more board support.

Last post by mamorani « Fri Mar 12, 2021 8:36 pm

by mamorani » Fri Mar 12, 2021 8:36 pm

0 Replies

157 Views

Last post by mamorani
Fri Mar 12, 2021 8:36 pm
'GenerateTopLevelWrapper'' has been removed. To generate RTL code without a top level wrapper, please select the ''Gener

Last post by mamorani « Fri Mar 12, 2021 8:36 pm

by mamorani » Fri Mar 12, 2021 8:36 pm

0 Replies

150 Views

Last post by mamorani
Fri Mar 12, 2021 8:36 pm
The ''FileName'' entered , is not a MATLAB File. Please make sure the file has a ''.m'' extension

Last post by mamorani « Fri Mar 12, 2021 8:35 pm

by mamorani » Fri Mar 12, 2021 8:35 pm

0 Replies

149 Views

Last post by mamorani
Fri Mar 12, 2021 8:35 pm
A resettable timing controller is not supported with FPGA-in-the-loop. To correct this issue, run ''hdlset_param( ''Tim

Last post by mamorani « Fri Mar 12, 2021 8:35 pm

by mamorani » Fri Mar 12, 2021 8:35 pm

0 Replies

154 Views

Last post by mamorani
Fri Mar 12, 2021 8:35 pm
The HDL Coder setting "Minimize clock enables" is set to "on". This might cause mismatch in the generated FPGA-in-the-Lo

Last post by mamorani « Fri Mar 12, 2021 8:35 pm

by mamorani » Fri Mar 12, 2021 8:35 pm

0 Replies

153 Views

Last post by mamorani
Fri Mar 12, 2021 8:35 pm
turn off HDL setting "Minimize clock enables

Last post by mamorani « Fri Mar 12, 2021 8:34 pm

by mamorani » Fri Mar 12, 2021 8:34 pm

0 Replies

168 Views

Last post by mamorani
Fri Mar 12, 2021 8:34 pm
FPGA-in-the-Loop does not support enum types on port

Last post by mamorani « Fri Mar 12, 2021 8:34 pm

by mamorani » Fri Mar 12, 2021 8:34 pm

0 Replies

147 Views

Last post by mamorani
Fri Mar 12, 2021 8:34 pm
External build is set along with Program Target Device. Setting these tasks together will result in either programming t

Last post by mamorani « Fri Mar 12, 2021 8:33 pm

by mamorani » Fri Mar 12, 2021 8:33 pm

0 Replies

171 Views

Last post by mamorani
Fri Mar 12, 2021 8:33 pm
For Zynq or Altera SoC reference design, the ''Ethernet'' programming method is deprecated, please use ''Download'' inst

Last post by mamorani « Fri Mar 12, 2021 8:32 pm

by mamorani » Fri Mar 12, 2021 8:32 pm

0 Replies

271 Views

Last post by mamorani
Fri Mar 12, 2021 8:32 pm
HDL Workflow file ' already exists. To overwrite it, pass the parameter ''Overwrite'', with the value true to export

Last post by mamorani « Fri Mar 12, 2021 8:32 pm

by mamorani » Fri Mar 12, 2021 8:32 pm

0 Replies

163 Views

Last post by mamorani
Fri Mar 12, 2021 8:32 pm
DUT ' and model ''HDLSubsystem'' do not match. Ignoring model value

Last post by mamorani « Fri Mar 12, 2021 8:31 pm

by mamorani » Fri Mar 12, 2021 8:31 pm

0 Replies

163 Views

Last post by mamorani
Fri Mar 12, 2021 8:31 pm
Task canceled. Please set a different project folder and run this task again.

Last post by mamorani « Fri Mar 12, 2021 8:31 pm

by mamorani » Fri Mar 12, 2021 8:31 pm

0 Replies

158 Views

Last post by mamorani
Fri Mar 12, 2021 8:31 pm

New Topic

3049 topics

Page 55 of 122
- Jump to page:
Previous
1
…
53
54
55
56
57
…
122
Next

Return to Board Index

Who is online

Users browsing this forum: No registered users and 9 guests

Forum permissions

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum